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Journal Articles Solid-State Electronics Year : 2024

Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Abstract

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current–voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs. We then incorporated these effects into the SPICE-compatible VNWFET compact model and further investigated the behaviors of trapping and electrothermal effects in basic logic circuits based on the compact model simulation.
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Year Month Jours
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Tuesday, May 21, 2024
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Tuesday, May 21, 2024
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Dates and versions

hal-04297709 , version 1 (21-11-2023)

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Y. Wang, Mukherjee Chhandak, H. Rezgui, M. Deng, J. Müller, et al.. Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors. Solid-State Electronics, 2024, 211, pp.108805. ⟨10.1016/j.sse.2023.108805⟩. ⟨hal-04297709⟩
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