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Optimisation de l'énergie dans une architecture mémoire multi-bancs pour des applications multi-tâches temps réel

Abstract : Several techniques were developed to reduce processor consumption which was considered as the dominant source of dissipation. However with the technology evolution and the increasing complexity of applications that make heavy use of large memory, the energy saving obtained by these techniques become limited. In fact these techniques focus on reducing only the energy consumption of the processor, ignoring their negative impact on the overall system energy consumption. Some studies showed that Dynamic Voltage Frequency Scaling technique (DVS), the most efficient technique to reduce the processor consumption, is responsible of an increase in the main memory consumption. This is due to two major reasons. The fist one is an increase of the number of tasks' preemptions when DVS is used on the processor and the second is a longer coactivity of the main memory with the processor execution. A multi-banked memory architecture, having the capability of setting banks in low power mode when they are not accessed keeping only the accessed bank in active mode, is adopted to reduce the memory consumption. Finding the main memory configuration (number of banks, size of banks) and the corresponding tasks allocation constitutes the major contribution of our study. Energy models of the main memory consumption developed at system level have identified several interdependent parameters. The strong interdependence of these parameters makes the problem NP-difficult. An exhaustive algorithm exploring all the configurations space was firstly developed. This technique allows to find the optimal solution and to analyze the behavior of the memory consumption according to the variations of tasks and system characteristics.
Although the exhaustive approach provides the optimal solution, the exploration space increases exponentially with the numbers of tasks. This approach remains interesting if it is employed off-line with a reduced number of tasks. An heuristic approach able to prune the configuration space and to efficiently resolve, in polynomial time, the power aware multi-bank main memory configuration and the corresponding tasks allocation is developed in a second step. The reduced complexity of the heuristic approach allows an on-line employment of this heuristic to perform tasks migration from one bank to another in case of dynamic applications where additional tasks are created during execution.
Several experimentations realized on signal processing real-time applications and on multimedia application (GSM and MPEG2) depict significative energy savings obtained on the main memory consumption. The memory configuration obtained by exhaustive exploration or by the heuristic approach coupled to a processor with DVS capability leads to an increase on the total energy saving.
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Submitted on : Wednesday, November 28, 2007 - 11:15:02 AM
Last modification on : Thursday, August 4, 2022 - 4:53:03 PM
Long-term archiving on: : Monday, April 12, 2010 - 5:22:16 AM


  • HAL Id : tel-00192473, version 1



Hanene Ben Fradj. Optimisation de l'énergie dans une architecture mémoire multi-bancs pour des applications multi-tâches temps réel. Automatique / Robotique. Université Nice Sophia Antipolis, 2006. Français. ⟨tel-00192473⟩



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